The use of copper wiring as interconnects in semiconductor devices has increased dramatically as ground rules shrink in order to reduce resistivity in the metal wiring. Interconnects are typically formed by a damascene approach in which a metal is deposited in an opening etched into one or more dielectric layers on a substrate. Although copper has a lower resistivity than Al or W, copper has a higher tendency to migrate into a dielectric layer. Therefore, a diffusion barrier layer such as Ta, TaN, Ti, or TiN is generally deposited on the sidewalls and bottom of an opening before depositing a copper layer. An important aspect of the damascene process is planarization of the metal and diffusion barrier layers so that they are coplanar with the top dielectric layer which is typically an interlevel dielectric layer (ILD). A CMP process is frequently employed as the preferred method to achieve planarization and involves a mechanical abrasive action as well as a chemical (etching) action. A CMP process may involve more than one CMP step. For example, a first CMP step may be used to substantially lower the level of the copper layer and then a second CMP step may be applied to remove the diffusion barrier layer above the dielectric layer. Finally, a third buffing step is commonly employed to reduce the amount of scratches on the substrate surface and improve planarity.
An example of a commercially available CMP tool is represented by tool 1 in FIG. 1. Tool 1 includes an upper carousel 2 that can rotate about a center post 3 on a center axis 4. Carousel 2 contains four rotatable carrier heads 5 that each holds a wafer 6. The base 7 of the CMP tool 1 is comprised of three polishing stations 8 and a transfer station 9. Each polishing station 8 has a rotatable platen 10 upon which a polishing pad 11 is placed and a mechanism for introducing a chemical slurry (not shown) that aids the polishing process. Typically, a wafer 6 is pressed against a polishing pad and slurry while the head 5 is rotated in one direction and the platen 9 is rotated in the opposite direction. Other solutions such as a deionized (DI) water rinse can be applied to the pad to remove the slurry before the wafer is transferred to another station. Other parts of the CMP tool 1 are not shown and may include an end point detect system to prevent excessive polishing of a metal or dielectric layer.
The CMP process has been improved by implementing methods to avoid defects such as scratches on the surface of the metal or dielectric layers, dishing, and copper corrosion. For example, corrosion is greatly reduced by treating the wafer including an exposed copper layer with an inhibitor solution containing benzotriazole (BTA) or the like. A method to prevent dishing is described in U.S. Pat. No. 6,503,828 and involves a polishing barrier layer that is formed over a copper layer and is patterned to protect the portion of the copper layer that is within a via or trench.
The number of particle or residue defects on a wafer after a conventional CMP buffing step remains a serious issue since the defects may reduce device yield and performance and lower reliability. These defects are comprised of particles or residues remaining from one or more slurries, particles or residues from the Cu or diffusion barrier layer, or a by-product of the chemical action between the slurry and one of the polished layers. In many cases the particle count is several thousand as determined by inspection with a defect monitor tool such as one available from Tencor, KLA, or Applied Materials.
In U.S. Pat. No. 6,395,635, a three step CMP process is followed by a two step buffing procedure applied to a dielectric layer to reduce residue and scratch defects on a tungsten damascene structure. The buffing procedure includes an oxide slurry followed by a DI water rinse and lowers the number of measured imperfections by about 50%.
Another method for removing residue in a tungsten CMP process is provided in U.S. Pat. No. 6,153,526 where a first tungsten CMP step is performed with a hard pad, a second oxide buffing step uses a soft pad, and a third short W CMP step involves a soft polishing pad. The third step is credited with removing oxide particles. A planarizing method for copper with reduced defects is disclosed in U.S. Pat. No. 6,432,826 where a first CMP step is performed to substantially lower the level of a copper layer, a buffing step is used to remove a diffusion barrier layer above an ILD, and a second buffing step is employed for a partial defect reduction. A final step that further lowers the defect count of stains and defects is treatment with a water solution containing citric acid, NH4OH, and optionally, a BTA corrosion inhibitor that removes about a 100 Angstroms thickness from the Cu surface and from the dielectric layer.
Existing oxide buffing processes are not effective in reducing particle and residue defects below a specified level that guarantees good device performance, especially for technology nodes approaching 100 nm and below. Therefore, a CMP procedure involving an improved oxide buffing process is required to achieve the low defect counts that are needed for advanced technologies.